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Technology Workshop – VLSI Design

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Course Features

  • Location: Janakpuri East New Delhi
  • Language: verilog/VHDL
  • Lesson: 0
  • Viewers: 1797
  • Prerequisites: No
  • Skill Level: Beginner
  • Course Capacity: 50
  • Start Course:

Descriptions

This is a basic program on VLSI(Very Large Scale Integration). Students will get good exposure of complete IC design flow. We will train students for developing digital logic design with hardware descriptive language Verilog HDL.
STEP

Eligibility

1st/2nd/3rd year students of B.E./B.Tech. from Electrical, Electronics, Computer Science. Recommended for First year engineering students.

Pre-requisites

Knowledge of Basics of Electronics, DigitalElectronics, C language programming

Features

  • Knowledge of VLSI Design Flow
  • Knowledge of Verilog HDL- RTL Coding & Synthesis
  • Knowledgeof Logical Verification and Designing.
  • Knowledge of FPGA
  • Personal Experience of working with Live

Benefits

  • Confidence build up for IC Design Methodology
  • Certification from EMTECH FOUNDATION,New Delhi
  • Fare understanding of Digital Logic Design
  • Fare understanding of FPGA Implementation
  • Experience of BEST learning practice
  • Acquire skills to do better Minor/Major Project
  • Can participate in various national/international competition and techfest

Curriculum

Section 1 : Introduction to VLSI Design

Section 2 : Overview of Digital Electronics

1. Number system

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2. Converters

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3. Boolean Algebra

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4. Logic gate

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5. K-Map

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Section 3 : Combinational Logic Design

6. Adder, Substracter

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7. Comparators

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8. Multiplexer, Demultiplexer

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9. Encoder, Decoder

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Section 4 : Sequential Logic Design

10. Latches

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11. Flip Flops

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12. Counters

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13. Registers

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Section 5 : Verilog HDLs Overview

14. Design hierarchy

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15. About HDL

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16. Advantage of HDL

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17. About Verilog

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18. Popularity of Verilog

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19. Level of abstraction

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Section 6 : Verilog Concepts

20. Lexical conversion

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21. Data types

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22. System task and compiler

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23. Definition of Module

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24. Declaration of ports

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Section 7 : Gate Level Modelling

25. About gate type modelling

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26. Delay concepts

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27. Examples

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Section 8 : Date Flow Modeling

28. About data flow modelling

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29. Assignment

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30. Delay control

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31. Operators

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32. Examples

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Section 9 : Behavioral Modelling

33. About behavioural modelling

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34. Structured procedures

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35. Initial and always

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36. Blocking and non- blocking statement

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37. Delay control

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38. Conditional statement

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39. Loops

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Section 10 : Tasks and Function

40. Difference between Tasks and Function

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41. Declaration of function

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42. Declaration of Tasks

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Section 11 : Modelling Technique

43. Assign and Deassign

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44. Force and Release

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Section 12 : User Defined Primitives

45. About UDP

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46. Rule for UDPs

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47. UDP instantiation

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Section 13 :Apply Stimulus

48. Need of TB

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49. About TB

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50. Type of TB

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51. Apply stimulus

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Section 14 :Finite State Machine

51. Definition of FSM

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52. About state machine

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53. Step to design

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Section 15 :ABOUT FPGA

55. Introduction to FPGA

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56. FPGA architecture

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57. Logic element

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58. Programmable Wiring

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59. Technology

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60. SRAM Based FPGA

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61. Configuration vs programming

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Section 16 :ABOUT FPGA

62. About synthesis

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63. Simulation vs synthesis

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64. How synthesis used

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65. What impact of logic synthesis

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66. Synthesis process

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Section 17 :Verification Technique

67. Formal verification

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68. Circuit verification

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Section 18 :Project work Preparation

69. Selection of project

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70. Software design of project

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71. Testing methods(Hardware/Software)

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Section 19 :Documentation

72. Preparation of synopsis

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73. Preparation of PPT

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74. Preparation of project report

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75. Preparation of code documentation

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76. Submission of documents

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